1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a gate driving circuit for an LCD device and a method of driving the LCD device using the same.
2. Discussion of the Related Art
Among the various types of flat panel display (FPD) devices, liquid crystal display (LCD) devices are widely used as monitors for notebook computers and desktop computers because of their excellent characteristics, such as light weight, portability and low power consumption. Specifically, active matrix type LCD devices having thin film transistors (TFTs) as switching elements are actively researched and developed because of their superiority in displaying moving images.
FIG. 1 is a schematic block diagram of a liquid crystal display device according to the related art, and FIG. 2 is a schematic view showing a liquid crystal display panel of the liquid crystal display device according to the related art. In FIGS. 1 and 2, the liquid crystal display device includes a liquid crystal display panel 2 and a liquid crystal module (LCM) driving circuit 26. The LCM driving circuit 26 includes an interface 10, a timing controller 12, a source voltage generator 14, a reference voltage generator 16, a data driver 18 and a gate driver 20. RGB data and timing sync signals, such as clock signals, horizontal sync signals, vertical sync signals and data enable signals, are input from an external driving system such as a personal computer to the interface 10. The interface 10 outputs the RGB data and the timing sync signals to the timing controller 12. For example, a low voltage differential signal (LVDS) interface and transistor logic (TTL) interface may be used for transmission of the RGB data and the timing sync signals. In addition, the interface 10 may be integrated in a single chip together with the timing controller 12.
A plurality of gate lines “GL1” to “GLn” and a plurality of data lines “DL1” to “DLm” are formed in the liquid crystal display panel 2 and are driven respectively by the gate driver 20 and the data driver 18. The plurality of gate lines “GL1” to “GLn” and the plurality of data lines “DL1” to “DLm” cross each other to define a plurality of pixel regions. For each pixel region P, a thin film transistor “TFT” is connected to the corresponding gate line and the corresponding data line, and a liquid crystal capacitor “LC” connected to the thin film transistor “TFT” is formed in each pixel region. The liquid crystal capacitor “LC” is turned on/off by the thin film transistor “TFT” to thereby modulate the transmittance of incident light through the pixel regions to display images.
The timing controller 12 generates data control signals for the data driver 18 that includes a plurality of data integrated circuits (ICs), and gate control signals for the gate driver 20 that includes a plurality of gate ICs. Moreover, the timing controller 12 outputs data signals to the data driver 18. The reference voltage generator 16 generates reference voltages using a digital-to-analog converter (DAC) in the data driver 18. The reference voltages are set up according to transmittance-voltage characteristics of the liquid crystal display panel 2. The data driver 18 determines the reference voltages for the data signals according to the data control signals and outputs the determined reference voltages to the liquid crystal display panel 2 to control a rotation angle of liquid crystal molecules of the liquid crystal capacitors.
The gate driver 20 controls the ON/OFF operation of the thin film transistors (TFTs) in the liquid crystal display panel 2 according to the gate control signals from the timing controller 12. The gate driver 20 sequentially enables the plurality of gate lines “GL1” to “GLn.” Accordingly, the data signals from the data driver 18 are supplied to the pixels in the pixel regions of the liquid crystal display panel 2 through the TFTs. The source voltage generator 14 supplies source voltages to elements of the LCD device and a common voltage to the liquid crystal display panel 2.
Although not shown in FIGS. 1 and 2, the liquid crystal display device includes a backlight assembly including at least one lamp. The backlight assembly emits light onto the liquid crystal display panel 2.
FIG. 3 is a schematic block diagram showing the gate driver of FIG. 1 according to the related art. As shown in FIG. 3, the gate driver 20 includes a plurality of related art shift register stages “SR1” to “SRn”. Each high level voltage (VDD), each low level voltage (VSS) and each clock signal (CLKs) are supplied to each shift register stage “SR1” to “SRn”. Moreover, a start voltage “Vst” is supplied to a first shift register stage “SR1”. The first shift register stage “SR1” outputs a first gate signal “Vg1” to a first gate line (of FIG. 2). The first gate signal “Vg1” output by the first shift register stage is provided as a start voltage of a second shift register “SR2”. The second shift register “SR2” outputs a second gate signal “Vg2” to a second gate line (of FIG. 2) in response to the first gate signal “Vg1” output by the first shift register stage. In a similar manner, the plurality of shift registers “SR1” to “SRn” sequentially supply a plurality of gate signals “Vg1” to “Vgn” to a plurality of gate lines “GL1” to “GLn” as shown in FIG. 4.
FIG. 4 is a timing chart showing gate signals of the gate driver according to the related art. As shown in FIG. 4, the plurality of related art shift register stages “SR1” to “SRn” (of FIG. 3) sequentially supply the gate signals “Vg1” to “Vg5” respectively to the gate lines “GL1” to “GL5”. Accordingly, a plurality of pixel TFTs “TFT” (of FIG. 2) connected to the plurality of gate lines “GL1” to “GL5” respectively, are sequentially turned on.
Each shift register stage “SR1” to “SRn” includes identical elements. As shown in FIG. 5, each of the shift register stages “SR1” to “SRn” includes pull-up and pull-down TFTs Tup and Tdn. The pull-up and pull-down TFTs Tup and Tdn each include an amorphous silicon layer as a semiconductor layer. If the pull-down TFT Tdn is driven under the high voltage for a long period of time, the pull-down TFT Tdn may be damaged.